This invention relates generally to semiconductor integrated circuit packaging and more particularly, it relates to a pin grid array package structure which has a higher packaging density, equalized signal delays and minimum cross-talk.
Due to the increasing commercial need of semiconductor integrated circuits which can perform more and more functions, semiconductor integrated circuit chips are becoming very large in size and dissipate large amounts of power. With the increased size and power requirements, there has also been an increase in the complexity and cost of providing interconnections and packaging for the semiconductor chips. In order to reduce cost and increase reliability, some interconnection designs of the prior art have provided insulator substrate such as ceramic or wiring boards on which are mounted the semiconductor chips or dies.
The metal conductors or traces on the wiring boards are generally used to interconnect bonding pads on an outer lead bonding area surrounding the die to the plurality of terminal pins. The traces in the prior art design are typically routed away from the outer lead bond area towards the outside edges of the package with either very long or very short interconnection traces to the various external pins. In other prior art designs, the traces are routed away from the outer lead bond area towards the die again with either very long or very short interconnection traces to the various external terminal pins. As a result, the very long trace lengths had an increased parasitic inductance and capacitance over the very short trace lengths. Further, this would create the problem of an electrical signal delay between the different traces or signal channels.
It would therefore be desirable to provide a pin grid array package structure which has a higher packaging density than those traditionally available. Further, it would be expedient to reduce the physical length of the very long traces so that the difference in lengths of all of the traces are less than the conventional pin grid array structures, thereby equalizing the electrical signal delay between different channels. This is accomplished in the present invention by the provision of a substrate or wiring board having a plurality of conductor runs in which first conductor runs extends outwardly from the bonding pads on the outer lead bond area and alternating second conductor runs extend inwardly from the bonding pads on the outer lead bond area. In addition, delay line (capacitance-loading) networks are formed in the conductor runs for further equalizing signal delay between the different conductor runs.